View IS61NP25618-133B2_3788029.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? 100 percent bus utilization no wait cycles between read and write internal self-timed write cycle individual byte write control single r/w (read/write) control pin clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining for tqfp power down mode common data inputs and data outputs cke pin to enable clock and suspend operation jedec 100-pin tqfp and 119 pbga packages single +3.3v power supply ( 5%) np version: 3.3v i/o supply voltage nlp version: 2.5v i/o supply voltage industrial temperature available description the 4 meg 'np' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. they are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defines the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 128k x 32, 128k x 36 and 256k x 18 pipeline 'no wait' state bus sram november 2002 fast access time symbol parameter -150 -133 -100 units t kq clock access time 3.8 4.2 5 ns t kc cycle time 6.7 7.5 10 ns frequency 150 133 100 mhz
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? block diagram adv we } bw ? x (x=a,b,c,d or a,b) ce ce2 ce2 control logic 128kx32; 128kx36; 256kx18 memory array write address register write address register control logic output register buffer address register a [0:16] or a [0:17] clk cke a2-a16 or a2-a17 a0-a1 a'0-a'1 burst address counter mode data-in register data-in register control register oe zz 32, 36 or 18 k k dqa0-dqd7 or dqa0-dqb8 dqpa-dqpd k k
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 nc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 nc a5 nc nc a4 a3 a2 gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a10 nc nc adv vcc nc ce oe nc we vcc clk nc cke a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd vcc a14 nc a16 ce2 a15 nc dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 nc a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 128k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a16 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwd synchronous byte write enable we write enable cke clock enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq i solated output buffer supply: +3.3v/2.5v zz snooze enable pin configuration 119-pin pbga (top view) 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 vcc vcc vcc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd vcc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 a6 a7 ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk we cke oe adv nc nc a8 a9
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 dqpc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 dqpd a5 nc nc a4 a3 a2 gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a10 nc nc adv vcc nc ce oe nc we vcc clk nc cke a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd vcc a14 nc a16 ce2 a15 dqpb dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 dqpa a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 pin configuration 119-pin pbga (top view) 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a16 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwd synchronous byte write enable we write enable cke clock enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v/2.5v zz snooze enable dqpa-dqpd parity data i/o 128k x 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 vcc vcc vcc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd vcc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 a6 a7 ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk we cke oe adv nc nc a8 a9
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? a b c d e f g h j k l m n p r t u vccq nc nc dq9 nc vccq nc dq12 vccq nc dq14 vccq dq16 nc nc nc vccq a6 ce2 a7 nc dq10 nc dq11 nc vcc dq13 nc dq15 nc dqp2 a5 a10 nc a4 a3 a2 gnd gnd gnd bwb gnd nc gnd nc gnd gnd gnd mode a11 nc nc adv vcc nc ce oe a17 we vcc clk nc cke a1 a0 vcc nc nc a8 a9 a12 gnd gnd gnd nc gnd nc gnd bwa gnd gnd gnd vcc a14 nc a16 ce2 a15 dqp1 nc dq7 nc dq5 vcc nc dq3 nc dq2 nc a13 nc nc vccq nc nc nc dq8 vccq dq6 nc vccq dq4 nc vccq nc dq1 nc zz vccq 1 2 3 4 5 6 7 pin configuration 119-pin pbga (top view) (b) 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwb synchronous byte write enable we write enable cke clock enable ce , ce2, ce2 synchronous chip enable oe output enable dq1-dq16 synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v/2.5v zz snooze enable dqp1-dqp2 parity data i/o dqp1 is parity for dq1-8; dqp2 is parity for dq9-16 256k x 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc nc nc vccq gnd nc nc dq9 dq10 gnd vccq dq11 dq12 vcc vcc vcc gnd dq13 dq14 vccq gnd dq15 dq16 dqp2 nc gnd vccq nc nc nc a10 nc nc vccq gnd nc dqp1 dq8 dq7 gnd vccq dq6 dq5 gnd vcc vcc zz dq4 dq3 vccq gnd dq2 dq1 nc nc gnd vccq nc nc nc mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a11 a12 a13 a14 a15 a16 a17 a6 a7 ce ce2 nc nc bwb bwa ce2 vcc gnd clk we cke oe adv nc nc a8 a9
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? pin configuration 119-pin pbga (top view) (b2) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adv synchronous burst address advance bwa - bwb synchronous byte write enable we write enable cke clock enable ce , ce2, ce2 synchronous chip enable oe output enable dq1-dq16 synchronous data input/output mode bu rst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v/2.5v zz snooze enable dqp1-dqp2 parity data i/o dqp1 is parity for dq1-8; dqp2 is parity for dq9-16 256k x 18 a b c d e f g h j k l m n p r t u vccq nc nc dq9 nc vccq nc dq12 vccq nc dq14 vccq dq16 nc nc nc vccq a ce2 a nc dq10 nc dq11 nc vcc dq13 nc dq15 nc dqp2 a a nc a a a gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode a nc nc adv vcc nc ce oe nc we vcc clk nc cke a1 a0 vcc nc nc a a a gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd vcc a nc a ce2 a dqp1 nc dq7 nc dq5 vcc nc dq3 nc dq2 nc a a nc vccq nc nc nc dq8 vccq dq6 nc vccq dq4 nc vccq nc dq1 nc zz vccq 1 2 3 4 5 6 7
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? synchronous truth table (1) address operation used cs cs cs cs cs 1 cs2 cs cs cs cs cs 2 adv we we we we we bw bw bw bw bw x oe oe oe oe oe cke cke cke cke cke clk not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation finally depends on status of asynchronous pins (zz and oe ). burst read deselect burst write begin read begin write read write read write burst burst burst ds ds ds read ds ds read write write burst burst write read state diagram
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? asynchronous truth table (1) operation zz oe oe oe oe oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x18) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. write truth table (x32/x36) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? interleaved burst address table (mode = v cc ) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) (mode = gnd) symbol parameter value unit t stg storage temperature ?65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ccq + 0.3 v v in voltage relative to gnd for ?0.3 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? operating range range ambient temperature d evice v cc v ccq commercial 0c to +70c 61npxxxxx 3.3v 5% 3.3v 5% 61nlpxxxxx 3.3v 5% 2.5v 5% industrial -40c to +85c 61npxxxxx 3.3v 5% 3.3v 5% 61nlpxxxxx 3.3v 5% 2.5v 5% power supply characteristics (1) (over operating range) -150 -133 -100 max max max symbol parameter test conditions x18 x32/36 x18 x32/36 x18 x32/36 uni t i cc ac operating device selected, com. 305 305 290 290 275 275 ma supply current oe = v ih , zz v il ,i nd . ? ? 305 305 290 290 all inputs 0.2v or v cc ? 0.2v, cycle time t kc min. i sb standby current device deselected, c om .9090 8080 7070 ma ttl input v cc = max., ind. ? ? 90 90 80 80 all inputs 0.2v or v cc ? 0.2v, zz v il , f = max. i sbi standby current device deselected, com. 10 10 10 10 10 10 ma cmos input v cc = max., ind. ? ? 15 15 15 15 v in gnd + 0.2v or v cc ? 0.2v f = 0 note: 1. mode pin has an internal pullup and should be tied to vcc or gnd. it exhibits 30 a maximum leakage current when tied to gnd + 0.2v or vcc ? 0.2v. dc electrical characteristics (over operating range) 2.5v 3.3v symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v v ccq ) 2.0 ? 2.4 ? v i oh = 1.0 ma (2.5v v ccq ) v ol output low voltage i ol = 8.0 ma (3.3v v ccq ) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v v ccq ) v ih input high voltage 1.7 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage ?0.3 0.7 ?0.3 0.8 v i li input leakage current gnd v in v cc (1) ?5 5 ?5 5 a i lo output leakage current gnd v out v ccq , oe = v i ?5 5 ?5 5 a
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 3.3v i/o output load equivalent z o = 50 ? 1.5v 50 ? output 317 ? 5 pf including jig and scope 351 ? output +3.3v figure 1 figure 2 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 3.3v.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 2.5v i/o output load equivalent z o = 50 ? 1.25v 50 ? output 1,667 ? 5 pf including jig and scope 1,538 ? output +2.5v figure 3 figure 4
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? read/write cycle switching characteristics (1) (over operating range) -150 -133 -100 symbol parameter min. max. min. max. min. max. unit fmax clock frequency ? 150 ? 133 ? 100 mhz t kc cycle time 6.7 ? 7.5 ? 10 ? ns t kh clock high time 2.5 ? 3 ? 3 ? ns t kl clock low time 2.5 ? 3 ? 3 ? ns t kq clock access time ? 3.8 ? 4.2 ? 5 ns t kqx (2) clock high to output invalid 1.5 ? 1.5 ? 1.5 ? ns t kqlz (2,3) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (2,3) clock high to output high-z ? 3 ? 3.5 ? 3.5 ns t oeq output enable to output valid ? 3.8 ? 4.2 ? 5 ns t oelz (2,3) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (2,3) output disable to output high-z ? 3.5 ? 3.5 ? 3.5 ns t as address setup time 1.5 ? 1.5 ? 1.5 ? ns t ws read/write setup time 1.5 ? 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? 1.5 ? ns t se clock enable setup time 1.5 ? 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? 1.5 ? ns t ds data setup time 2.0 ? 2.0 ? 2.0 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t he clock enablehold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t advh address advance hold time 0.5 ? 0.5 ? 0.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t pds zz high to power down ? 2 ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? sleep mode timing don't care deselect or read only deselect or read only t rzzi k zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z sleep mode electrical characteristics symbol parameter conditions mi n. max. unit i sb 2 current during sleep mode zz vih 10 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? read cycle timing t ds clock adv a16 - a0 or a17 - a0 we cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined notes: we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? write cycle timing t ds t dh clock adv a16 - a0 or a17 - a0 we cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined notes: we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz q0-3 q0-4
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? single read/write cycle timing clock cke address write cs adv oe data out data in d5 t se t he t kh t kl t kc don't care undefined notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? cke cke cke cke cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clock cke address write cs adv oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? cs cs cs cs cs operation timing don't care undefined clock cke address write cs adv oe data out data in t se t he t kh t kl t kc notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l d5 d2 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? ordering information (61npxxxxx) commercial range: 0c to +70c frequency order part number package 128kx32 150 is61np12832-150tq tqfp 133 is61np12832-133tq tqfp 100 is61np12832-100tq tqfp 128kx36 150 is61np12836-150tq tqfp is61np12836-150b pbga 133 is61np12836-133tq tqfp is61np12836-133b pbga 100 is61np12836-100tq tqfp 256kx18 150 is61np25618-150tq tqfp is61np25618-150b2 pbga 133 is61np25618-133tq tqfp IS61NP25618-133B2 pbga 100 is61np25618-100tq tqfp industrial range: -40c to +85c frequency order part number package 128kx32 133 is61np12832-133tqi tqfp 133 is61np12832-133bi pbga 128kx36 133 is61np12836-133tqi tqfp 133 is61np12836-133bi pbga 256kx18 133 is61np25618-133tqi tqfp 133 IS61NP25618-133B2i pbga
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 rev. b 11/21/02 is61np12832 is61np12836 is61np25618 is61nlp12832 is61nlp12836 is61nlp25618 issi ? ordering information (61nl pxxxxx) commercial range: 0c to +70c frequency order part number package 128kx32 133 is61nlp12832-133tq tqfp is61nlp12832-133b pbga 128kx36 133 is61nlp12836-133tq tqfp is61nlp12836-133b pbga 150 is61nlp12836-150tq tqfp is61nlp12836-150b pbga 256kx18 133 is61nlp25618-133tq tqfp is61nlp25618-133b pbga is61nlp25618-133b2 pbga 150 is61nlp25618-150tq tqfp is61nlp25618-150b2 pbga industrial range: -40c to +85c frequency order part number package 128kx32 133 is61nlp12832- 133tqi tqfp 128kx36 133 is61nlp12836- 133tqi tqfp 133 is61nlp12836-133bi pbga 256kx18 133 is61nlp25618- 133tqi tqfp 133 is61nlp25618-133b2i pbga

▲Up To Search▲

Price & Availability of IS61NP25618-133B2

	To Download IS61NP25618-133B2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .